1. Field of the Invention
The present invention relates to a highly integrated and high performance semiconductor device having transistors formed in a semiconductor layer on an insulating surface and a method for manufacturing the same.
The present invention also relates to a semiconductor device and more particularly to a lateral bipolar transistor structure and a method for manufacturing the same.
2. Related Background Art
In a prior art silicon wafer bulk process, a vertical bipolar transistor is manufactured in a manner shown in FIG. 28. In FIG. 28, numeral 301 denotes a first vertical npn-type bipolar transistor, numeral 302 denotes a second npn-type bipolar transistor, and numeral 303 denotes a device isolation region for electrically isolating the bipolar transistor 301 and the bipolar transistor 302. In FIG. 28, a collector of the bipolar transistor 301 and an emitter of the bipolar transistor 302 are electrically connected by an electric conductor 315. Numeral 304 denotes a p-type silicon substrate, numerals 305 and 305' denote n.sup.+ -type regions which serve as collector regions of the bipolar transistors 301 and 302, respectively, numeral 306 denotes an n.sup.- -type epitaxial region, numeral 307 denotes a p-type region for electrically isolating the bipolar transistor 301 and the bipolar transistor 302, numeral 308 denotes a selective oxidization region, numerals 309 and 309' denote collector lead layers, numerals 310 and 310' denote p-type base regions, numerals 311 and 311' denote n.sup.+ -type emitter regions, numeral 312 denotes an interlayer insulating layer, numerals 313, 314, 315, 316 and 317 denote Al (aluminum) electrodes, and numeral 318 denotes a passivation insulating layer.
In a prior art silicon wafer bulk process, a lateral bipolar transistor is manufactured in a manner shown in FIG. 29. In FIG. 29, numeral 321 denotes a first lateral pnp-type bipolar transistor, numeral 322 denotes a second lateral pnp-type bipolar transistor, and numeral 323 denotes a device isolation region for electrically isolating the bipolar transistor 321 and the bipolar transistor 322. In FIG. 29, a collector of the bipolar transistor 321 and an emitter of the bipolar transistor 322 are electrically connected by a wiring 335. Numeral 324 denotes a p-type silicon substrate, numerals 325 and 327 denote n.sup.+ -type regions which serve as base regions of the bipolar transistors 321 and 322, respectively, numeral 326 denotes an n.sup.- -type epitaxial region, numeral 327 denotes a p-type region for electrically isolating the bipolar transistor 321 and the bipolar transistor 322, numeral 328 denotes a selective oxidization region, numerals 329 and 329' denote base lead layers, numerals 330 and 330' denote p.sup.+ -type emitter regions, numerals 331 and 331' denote p.sup.+ -type collector regions, numeral 332 denotes an interlayer insulating layer, numerals 333, 334, 335, 336 and 337 denote Al electrodes, and numeral 338 denotes a passivation insulating layer.
In the prior art vertical bipolar transistor described above, a hetero-junction bipolar transistor has been known which uses a mixed crystal semiconductor Si.sub.(1-X) Ge.sub.X (where X is a crystal mixture ratio) as a base region in order to enhance an operation speed of the transistors. When the base region is made of SiGe mixed semi-conductor 1 hetero-junction bipolar transistor having a narrow gap base region is the result. In order to make this narrow gap base region in an npn transistor, usually epitaxial growth of a p-type SiGe is used. However, the following problems are encountered.
(1) A defect may be easily produced because of an abrupt change of composition at the interface of the Si substrate and the Si.sub.(1-X) Ge.sub.X layer.
(2) Compatibility with the existing manufacturing process is poor. For example, when a Bi-CMOS circuit combined with MOS transistors and bipolar transistors are to be manufactured, the process is very complex.
On the other hand in order, to enhance an operation speed of the transistors, a lateral bipolar transistor is formed on an Si substrate. However, the manufacturing process is more complex than that for a vertical bipolar transistor if a narrow gap base is to be formed.
Further, in the prior art hetero-junction bipolar transistor, either lateral or vertical, which is made by epitaxial growth, the interface between the Si crystal which forms the emitter region and Si.sub.(1-X) Ge.sub.X which forms the base region corresponds to the interface between the emitter and the base or the interface between the base and collector. As a result, lattice defects such as point defects or dislocations, both of which serves as the centers of the electrical recombination, is produced in the vicinity of a junction interface of the emitter and the base or in the vicinity of a junction interface of the base and the collector, so that the base current of the bipolar transistor increases and the current amplification factor h.sub.FE decreases.
In order to increase operation speed of a bipolar transistor, a heterobipolar transistor with the above described narrower base region may be provided. Also, a structure wherein the Si region is formed on an insulating layer (substrate) (SOI structure) and a lateral bipolar transistor is formed on the Si region may be used therefor. This is because when a transistor is formed on an insulating layer, the transistor with a reduced parasitic capacitance in relation to a substrate, and without latch-up can be provided. In such SOI lateral type bipolar transistor of npn type, for example, the Si region operating as a base is doped with ions such as B, thereby forming the base region into a p-type layer. FIG. 30 shows the above described structure. 4 denotes an insulating layer. 5 denotes n.sup.- -type silicon layer formed on an insulating film 4. 6 denotes a selective oxidation layer. 8 denotes a p-type polysilicon layer operating as a base extraction electrode. 10 denotes an n.sup.+ -type region operating as an emitter. 11 denotes an n.sup.+ -type region operating as a collector. 12 denotes a p-type region operating as a base. 14 denotes an emitter electrode. 15 denotes a collector electrode. 16 denotes a base electrode.
However, in the case of the above described structure, the p-type polysilicon 8 operating as the base extraction electrode and p-type Si 12 operating as the base region have energy band gaps at substantially the same potential level. Accordingly, a carrier flowing through the base regions would flow into the base electrode. The base current would be made greater, and thus cause a problem of undesirably greater h.sub.FE.
Further, in the prior art vertical and lateral bipolar transistors on the Si substrate, the device isolation region is required to electrically isolate the adjacent bipolar transistors. As a result, the integration density cannot be increased.
Further, in the prior art vertical and lateral bipolar transistors on the Si substrate, contacts and electric conductors are required to connect collectors, emitters or a collector and an emitter of adjacent bipolar transistors. As a result, contact resistances, wiring resistances and wiring capacitances are included in a load so that an operation speed of the transistor is restricted.
Further, when the hetero-junction bipolar transistor having the narrow gap base region of the lateral bipolar transistor is manufactured, the base regions 325 and 325' shown in FIG. 29 are formed by epitaxially growing Si.sub.(1-X) Ge.sub.X and then doping with an impurity which is of the opposite conductivity type to that of the gate region in the emitter and collector regions. In this process, however, it is difficult to increase the impurity concentration of the base region so that it is not possible to reduce a carriage base running time (.tau..sub.B), because the carrier base running time .tau..sub.B is given by: EQU .tau..sub.B =W.sub.B.sup.2 /nD.sub.B
where W.sub.B represents a base length, D.sub.B represents a diffusion coefficient and n represents a carrier concentration. In this case, a cutoff frequency of the transistor is substantially inversely proportional to the carrier base running time .tau..sub.B. Accordingly, in the prior art lateral bipolar transistor, the cutoff frequency f.sub.T cannot be increased because the carrier concentration cannot be increased. As a result, the operation speed of the lateral transistor cannot be increased.
It has been known that a high speed operation is attained when a MOS transistor is manufactured by using a SOI (silicon on insulator) with a semiconductor film thickness of 5000 .ANG. or less because a substrate capacitance is reduced in the SOI so that high speed turn-on and turn-off may be attained, however, when a circuit is constructed by only MOS structures, a design is restricted when a drive current is required.
Accordingly, in the SOI, a Bi-CMOS which is a combination of MOS and bipolar transistors is attracting notice, because in an SOI having a thin insulating film, the process is easier when lateral bipolar transistors are to be built in then when vertical bipolar transistors are to be built-in. However, the prior art lateral bipolar transistor is inferior in the operating speed to the vertical bipolar transistor.